#! /apps/mentor/aoi_cal_2018.4_17.10/bin/python3
import sys

def get_pin_lef(path):
	f1 = open(path,'r')
	string = "PIN"
	alist = []
	lines = f1.readlines()
	for i in lines:
		if string in i:
			alist.append(i[6:-1])
	f1.close()
	
	return sorted(alist)

def get_pin_verilog(string_list,path):
	f1 = open(path,'r')
	return_list = []
	f1_tell = 0
	a = 1
	while(a):
		line = f1.readline()
		if (string_list[1]+' '+string_list[0]) in line:
			f1_tell = f1.tell()
			a = 0
	f1.seek(f1_tell)
	a = 1
	string = ''
	while(a):
		line = f1.readline()
		if line == "\n":
			continue
		string += line.replace("\n",'')
		if string[-1] == ',':
			continue
		if (string_list[2] in string) and is_prefix(string_list[2],string):
			a = 0
		else :
			for i in string_list[3:]:
				if (i in string) and is_prefix(i,string):
					clean_string_verilog(string,return_list,i)
		string = ''
	f1.close()
	return sorted(return_list)

def get_pin_lib(path):
	f1 = open(path,'r')
	key_string = ["pin","pg_pin"]
	return_list = []
	lines = f1.readlines()
	for line in lines:
		for key in key_string:
			if (key in line) and is_prefix(key,line):
				clean_string_lib(return_list,line,key)
	return sorted(return_list)

def get_pin_sch(path, key_string):
	f1 = open(path,'r')
	return_list = []
	lines = f1.readlines()
	key = ".SUBCKT "+key_string+" "
	astr = ""
	aa = 0
	print(key)
	for line in lines:
		if (aa == 1):
			if ('+' in line):
				str1 = line.replace('+','').replace('\n','')
				astr += str1
			else:
				break
		if (key in line):
			str1 = line.replace(key,'').replace('\n','')
			print(str1)
			astr += str1
			aa = 1
	clean_string_sch(return_list,astr)
	return sorted(return_list)

def clean_string_sch(alist,string):
	blist = string.split(' ')
	for pin in blist:
		alist.append(pin)				
	
def clean_string_lib(alist,string,key_string):
	string = string.split('{')[0]
	string = string.replace(key_string,'').replace(' ','')
	alist.append(string[2:-2])

def is_prefix(string_a,string_b):
	len_stringb = len(string_b)
	len_stringa = len(string_a)
	is_f = 1
	for i in range(len_stringb):
		if string_b[i] == ' ':
			pass
		else:
			if string_a in string_b[i:i+len_stringa]:
				return True
			else:
				return False

def clean_string_verilog(line_string,return_string,string_i):
	string = line_string.split(';')[0]
	string = string.replace(" ",'').replace(string_i,'').replace('\t','')
	if ',' in string:
		a = string.split(',')
		for i in a:
			return_string.append(i)
	elif '[' in string:
		a = string.split(']')[0].split('[')[-1]
		b = int(a.split(':')[0])
		c = int(a.split(':')[-1])
		d = string.split(']')[-1]
		if b > c :
			for i in range(c,b+1):
				return_string.append(d+'['+str(i)+']')
		else :
			for i in range(b,c+1):
				return_string.append(d+'['+str(i)+']')
	else :
		return_string.append(string)


def is_match(alist,blist):
	is_match = 0
	not_match_list = []
	for i in alist:
		for j in blist:
			if i==j :
				#print("the"+i+"is match")
				is_match = 1
		if is_match==0 :
			#print("the "+i+" not match")
			not_match_list.append(i)
		is_match = 0
	return not_match_list



	
if ( 0 ): 
	print("=========the lib pin==========")
	path_lib = "/designs/cascade/ip/ig/NDPHY_SPEEDPLUS_FC/rev2.3.1/lib/ND_VREF_tt_0p75v_25c_typical.lib"
	list_lib = get_pin_lib(path_lib)
	print(len(list_lib))
	print(list_lib)
	print()


if ( 0 ):
	print("========the lef pin===========")
	block_name = ["DDR_VGEN_H","DDR_VGEN","DDR_IO_SUBPHY_11_H","DDR_IO_SUBPHY_11","DDR_INGVSS_H","DDR_INGVSS","DDR_CAL_H","DDR_CAL","DDR_ASYNC","DDR_ASYNC_H"]
	#idex = "DQ_BIT_H"
	#idex = "DQS_BIT"
	#idex = "DQS_BIT"
	path_lef = "/designs/cascade/ip/ig/NDPHY_SPEEDPLUS_FC/rev2.3.1/lef/ND_VREF.lef"
	print(path_lef)
	list_lef = get_pin_lef(path_lef)
	print(len(list_lef))
	print(list_lef)
	print()

if ( 0 ):
	print("=========the verilog pin=======")
	path_verilog = "/projects/tacoma12/workspace/xwqiu/cadence/virtuoso/datain/DDR_IO_SUBPHY_11_H.v"
	print(path_verilog)
	# key_string[0] is module name
	idex = "DDR_IO_SUBPHY_11_H"
	key_string = [idex,"module","endmodule","input","output","inout"]
	list_verilog = get_pin_verilog(key_string,path_verilog)
	print(len(list_verilog))
	print(list_verilog)
	print()

if ( 0 ):
	print("=========the schematic pin=======")
	path = "/projects/tacoma12/workspace/xwqiu/cadence/virtuoso/netlist/220928/"
	module = "P12QSDDR_H"
	path_schematic = path+module+".v"
	list_schematic = get_pin_sch(path_schematic,module)
	print(len(list_schematic))
	print(list_schematic)
	print()

if ( 0 ):
	print("==========yes or not match========")
	print(list_lib==list_lef)
	print(is_match(list_lib,list_lef))
	print()
if ( 0 ):
	print("==========yes or not match========")
	print(list_verilog==list_lef)
	print("pin in verilog but not in lef")
	match_vlog_lef = is_match(list_verilog,list_lef)
	print(len(match_vlog_lef))
	print(match_vlog_lef)
	print()
	print("pin in lef but not in verilog")
	match_lef_vlog = is_match(list_lef, list_verilog)
	print(len(match_lef_vlog))
	print(match_lef_vlog)
	print()


if ( 0 ):
	path_lef_old = "/projects/tacoma12_a0/workspace/xwqiu/chip_top/innovus_0907/chip_top/chip_top_RDL_from_gao_230203_gloded.dat/libs/lef/pcie_wrap_top.lef"
	path_lef_new = "/projects/tacoma12_a0/workspace/xwqiu/chip_top/innovus_0907/toRDL/block_LEF/pcie_wrap_top.20230215.lef"
	list_lef_old = get_pin_lef(path_lef_old)
	list_lef_new = get_pin_lef(path_lef_new)
	
#	print(list_lef_old)
#	print(list_lef_new)

	print("pin in lef_old but not in lef_new")
	print(is_match(list_lef_old,list_lef_new))
	print("pin in lef_new but not in lef_old")
	print(is_match(list_lef_new,list_lef_old))
	print()



if ( 1 ):
	
	name = sys.argv[1]

	if ( 1 ): 
		print("=========the lib pin==========")
		#path_lib = "/designs/cascade/ip/ig/NDPHY_SPEEDPLUS_FC/rev2.3.1/lib/"+name+"_tt_0p75v_25c_typical.lib"
		#path_lib = "/designs/cascade/ip/ig/DDRPHY/rev2.8.0/lib/"+name+"_tt_0p75v_25c_typical.lib"
		#path_lib = "/designs/cascade/ip/ig/OSC2M/rev1.1/lib/OSC2M_tt_0p75v_25c_typical.lib"
		path_lib = "/designs/cascade/ip/ig/CAB/rev1.3.1/lib/CAB_tt_0p75v_25c_typical.lib"
		list_lib = get_pin_lib(path_lib)
		print(len(list_lib))
		print(list_lib)
		print()


	if ( 1 ):
		print("========the lef pin===========")
		block_name = ["DDR_VGEN_H","DDR_VGEN","DDR_IO_SUBPHY_11_H","DDR_IO_SUBPHY_11","DDR_INGVSS_H","DDR_INGVSS","DDR_CAL_H","DDR_CAL","DDR_ASYNC","DDR_ASYNC_H"]
		#path_lef = "/projects/analog_ip/workspace/xwqiu/cl/tacoma6/IP/NDPHY/lef/"+name+".lef"
		#path_lef = "/projects/analog_ip/workspace/xwqiu/cl/tacoma6/IP/DDRPHY/lef/"+name+".lef"
		path_lef = "/projects/analog_ip/workspace/xwqiu/cl/tacoma6/IP/CAB/lef/CAB.lef"
		print(path_lef)
		list_lef = get_pin_lef(path_lef)
		print(len(list_lef))
		print(list_lef)
		print()

	print("==========yes or not match========")
	print(list_lib==list_lef)
	print("in lib but not in lef!")
	print(is_match(list_lib,list_lef))
	print()

	print(list_lib==list_lef)
	print("in lef but not in lib!")
	print(is_match(list_lef,list_lib))
	print()
